1. Field of the Invention
The present invention relates to a format converter and, more particularly, a format converter for displaying RGB picture signals, having different video modes, received from a fixed dimensional display device.
2. Discussion of Related Art
An excessive power consumption is generally attended on the display monitor having a CRT (Cathode Ray Tube) and widely used to display pictures applied from a computer's main body with a high voltage. The display monitor having great volume due to the CRT is hard to be carried or moved about. To overcome this problem with the conventional display monitor, a TFT (Thin Film Transistor) LCD fabricated in a similar manner as semiconductors has been developed and now is generally termed FPD (Flat Panel Display).
Various types of FPD such as PDP (Plasma Display Panel), LCD (Liquid Crystal Display), and LEDD (Light Emitting Diode Display) have been developed for common uses. Out of these FPDs, the latest one is the LCD device that is currently used as a portable monitor in a notebook computer. Some LCD devices are greatly developed to be of such a size as to display pictures through the screen of a common television.
Below is a description of the construction of an LCD monitor circuit that is most widely used as an FPD monitor, with reference to FIG. 1. Referring to FIG. 1, a PC 100 includes a CPU 110 for receiving and processing a keyboard signal input by a user, and for generating data according to the processed result, and includes a video card 120 for receiving the data generated by CPU 110, processing it as a RGB video signal, and outputting a horizontal synchronous signal H-SYNC and a vertical synchronous signal V-SYNC for synchronizing the video signal.
A LCD monitor 200 receiving the RGB video signal, horizontal and vertical synchronous signals H-SYNC and V-SYNC from video card 120 in PC 100 includes: an amplifier 201 for receiving the RGB video signal from video card 120, and amplifying it; a first analog/digital converter (A/D converter) 202 for converting the analog RGB video signal output from amplifier 201 to a digital video signal; a synchronous signal detector 203 for separately detecting horizontal and vertical synchronous signals W/V-SYNC output from video card 120; a first phase locked loop (PLL) 204 for receiving horizontal and vertical synchronous signals H/V-SYNC detected by synchronous signal detector 203 and generating a clock frequency according to the horizontal and vertical synchronous signals; a microcomputer 205 which contains a digital/analog converter (D/A converter) for converting a digital signal to an analog signal, and generates on screen display (OSD) data; an OSD unit 206 for receiving the OSD data from microcomputer 205, and outputting the OSD data as an OSD signal; a second A/D converter 207 for receiving the OSD signal from OSD unit 206, and converting the OSD signal to a digital signal; a multiplexer 208 for receiving the OSD signal from second A/D converter 207 and RGB video signal from first A/D converter 202, and selectively outputting them; a first gate array 209 for setting output timing of the video signal and OSD signal selectively output from multiplexer 208; a second gate array 210 for storing and converting the RGB video signal output from first gate array 209; and a LCD panel 211 for receiving the video signal from second gate array 210, and displaying it.
The operation of the aforementioned conventional LCD monitor is explained below. When a user inputs data into PC 100 in order to execute a program, CPU 110 executes the program according to the data, and outputs video data according to the executed result to video card 120. Video card 120 processes the video data to generate a video signal. Video card 120 also generates horizontal and vertical synchronous signals HV-SYNC for synchronizing the RGB video signal. The video signal is sent from video card 120 to amplifier 201 which amplifies the video signal. The amplified video signal is an analog signal and is converted into a digital RGB video signal by first A/D converter 202, and the digital video signal is sent to multiplexer 208.
Synchronous signal detector 203 detects horizontal and vertical signals H/lI-SYNC for synchronizing the video signal output from video card 120 in PC 100, and sends the detected signals to PLL 204. PLL 204 outputs a predetermined clock frequency using the horizontal and vertical synchronous signals. The clock frequency is applied to A/D converter 202. The analog RGB video signal is sampled by A/D converter 202 according to the clock frequency, and the sampled video signal, i.e., the digital RGB video signal, is sent to multiplexer 208.
Microcomputer 205 containing an OSD control program and, in response to a received OSD control signal (not shown), generates the OSD signal according to the OSD control signal. The OSD signal is an analog signal and is converted into a digital signal by second A/D converter 207.
Multiplexer 208 receives the digital OSD signal output from second A/D converter 207, and digital RGB video signal output from first A/D converter 203. The digital OSD signal and digital RGB video signal are selectively output according to a selection signal (not shown) applied to multiplexer 208. For example, when the user uses control buttons (not shown) of LCD monitor 200 in order to display the OSD picture, an OSD selection signal from the control buttons of LCD monitor 200 is output through microcomputer 205 and OSD unit 206. The OSD selection signal is converted into a digital signal by second A/D converter 207, and sent to multiplexer 208 which selectively outputs the OSD signal according to the OSD selection signal.
When the OSD selection signal is not applied to multiplexer 208, multiplexer 208 outputs the digital RGB video signal applied from first A/D converter 203. The digital RGB video signal and digital OSD signal selectively output from multiplexer 208 are sent to first gate array 209. First gate array 209 receives the horizontal and vertical synchronous signals from PLL 204, and sets the output timing according to the horizontal and vertical synchronous signals. When the OSD function is employed, first gate array 209 outputs the digital OSD signal instead of the digital RGB video signal as a predetermined position of the LCD picture, using the horizontal and vertical synchronous signals.
Peak-to-peak voltage of the video signal generated from video card 120 is 0.7Vpp while peak-to-peak voltage of the OSD signal output from OSD unit 206 is 5Vpp. Thus, when multiplexer 208 switches the digital RGB video signal and the digital OSD signal, the signal processing becomes impossible because they are of different voltage values. To solve this, the peak-to-peak voltage of the video signal is amplified by amplifier 201 to 5Vpp.
The output timing of the digital RGB video signal selectively output by multiplexer 208 is controlled by first gate array 209. The digital RGB video signal output from first gate array 209 is stored and converted by second gate array 210, and then sent to LCD panel 211 which displays the digital RGB video signal. The resolution of an LCD monitor on which the RGB picture signals are displayed can be 640.times.480 for the VGA (Video Graphics Array) mode, 800.times.600 for the SVGA (Super Video Graphics Array) mode, 1024.times.768 for the XGA (Extended Graphics Array) mode, or 1280.times.1024 for the EWS mode. The resolution of the SVGA (800.times.600) mode means that the LCD monitor contains 800 pixels on the horizontal line and 600 pixels on the vertical line.
The conventional LCD monitor picture is further explained below with reference to the attached drawings. FIGS. 2A-2C show display pictures of a SVGA LCD monitor when video signals having different resolutions are input thereto. FIG. 2A illustrates the display of a picture according to the basic mode set in the SVGA LCD monitor, and in FIG. 2B the dotted lines illustrate a picture of a video signal having the XGAC (1024.times.768) video mode applied to the SVGA LCD monitor. In FIG. 2B, the object is displayed larger than the screen size can accommodate. In FIG. 2C the dotted lines illustrate a picture of a video signal in EWS (1280.times.1024) video mode applied to the SVGA LCD monitor. In FIG. 2C, the object is displayed even larger than the screen size can accommodate. Thus, the user cannot see a portion of the picture, which is displayed on the region beyond the monitor picture.
As described above, the prior art LCD monitor can be operated only in a single display mode of VGA, SVGA, XGA, or the like so that the object in another mode different from the display mode of the LCD monitor will appear smaller or larger than desired.